Publications

2023

1. IEEE

   A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers

   Sein Oh, Seunga Park, Yoontae Jung, and 4 more authors

   In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2. IEEE

   A 187dB FoMS 46fJ/Conv. 2nd-order Highpass Δ∑ Capacitance-to-Digital Converter (*Co-first authors)

   Yoontae Jung*, Sein Oh*, Jimin Koo, and 5 more authors

   In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
3. IEEE

   A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter

   Yoontae Jung, Jimin Koo, Sein Oh, and 4 more authors

   In 2023 IEEE Custom Integrated Circuits Conference (CICC), 2023
4. IEEE

   A 16-Channel Impedance-Readout IC With Synchronous Sampling and Baseline Cancelation for Fast Neural Electrical Impedance Tomography

   Ji-Hoon Suh, Haidam Choi, Yoontae Jung, and 7 more authors

   IEEE Solid-State Circuits Letters, 2023
5. IEEE

   A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current

   Donghee Cho, Hyungjoo Cho, Sein Oh, and 4 more authors

   IEEE Journal of Solid-State Circuits, 2023

2022

1. IEEE

   A Synchronous-Sampling Impedance-Readout IC with Baseline-Cancellation-Based Two-Step Conversion for Fast Neural Electrical Impedance Tomography

   Ji-Hoon Suh, Haidam Choi, Yoontae Jung, and 7 more authors

   In 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022
2. IEEE

   A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation

   Donghee Cho, Hyungjoo Cho, Sein Oh, and 4 more authors

   In 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022

2021

1. MDPI

   Conception and Simulation of a 2-Then-1-Bit/Cycle Noise-Shaping SAR ADC

   Kihyun Kim, Sein Oh, and Hyungil Chae

   Electronics, 2021

   Abs

   A 2-then-1-bit/cycle noise-shaping successive-approximation register (SAR) analog-to-digital converter (ADC) for high sampling rate and high resolution is presented. The conversion consists of two phases of a coarse 2-bit/cycle SAR conversion for high speed and a fine 1-bit/cycle noise-shaping SAR conversion for high accuracy. The coarse conversion is performed by both voltage and time comparison for low power consumption. A redundancy after the coarse conversion corrects the error caused by a jitter noise during the time comparison. Additionally, a mismatch error between signal and reference paths is eliminated with the help of a tail-current-sharing comparator. The proposed ADC was designed in a 28 nm CMOS process, and the simulation result shows a 68.2 dB signal-to-noise distortion (SNDR) for a sampling rate of 480 MS/s and a bandwidth of 60 MHz with good energy efficiency.

2. IEEE

   A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1

   Donghee Cho, Hongseok Shin, Hyunwoo Park, and 5 more authors

   In ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021
3. IEEE

   An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1–2 MASH Structure

   Sein Oh, Younggyun Oh, Juyong Lee, and 4 more authors

   IEEE Journal of Solid-State Circuits, 2021
4. IEEE

   An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC

   Soon-Jae Kweon, Joonho Gil, Chulhyun Park, and 9 more authors

   In 2021 Symposium on VLSI Circuits, 2021

2020

1. MDPI

   Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

   Juyong Lee, Younggyun Oh, Sein Oh, and 1 more author

   Sensors, 2020

   Abs

   A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm2, and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

2. IET

   Bandpass ΔΣ ADC using pipelined SAR ADC

   Sein Oh, Kim Kihyun, and Hyungil Chae

   Electronics Letters, 2020

   Abs

   This Letter proposes a second-order bandpass ΔΣ ADC using a pipelined successive-approximation-register (SAR) ADC as an internal quantiser. The second-order bandpass noise-shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure. The proposed ADC can show very high resolution even with low-order noise-shaping and low oversampling ratio. Also, it shows good energy efficiency and a high sampling rate due to the use of a pipelined SAR ADC as a quantiser.

3. IEEE

   A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1–2 MASH structure

   Sein Oh, Younggyun Oh, Juyoung Lee, and 4 more authors

   In 2020 IEEE Custom Integrated Circuits Conference (CICC), 2020

2019

1. IEICE

   4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor

   Sein Oh, Dong-young Hwang, and Hyungil Chae

   IEICE Electronics Express, 2019

2018

1. JEES

   Sensitivity Enhancement of a Vertical-Type CMOS Hall Device for a Magnetic Sensor

   Sein Oh, Byung-Jun Jang, and Hyungil Chae

   J. Electromagn. Eng. Sci, 2018